3 ms·
B extention does add have 'cmov' see: https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf https://raw.githubusercontent.com/riscv/
by panick21_ 4y ago
B extention does add have 'cmov' see:
https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf https://raw.githubusercontent.com/riscv/riscv-bitmanip/maste...
If you do instruction fusion, you might be able to transform the typical pairs that would create a short branch and simply convert them into a cmov micro-instruction. That it does not make the branch predictor much more complex.
- brucehoult 4y agoThat's a draft, containing instructions under consideration for inclusion. The ternary instructions didn't pass the test for utility vs cost and were not ratified. For example `cmix` only replaces three other instructions, two of which can be done in parallel. Emulating `cmov` is slightly more expensive: generate an all-1s or all-0s mask from your condition (e.g. `slt mask,a,b; neg mask,mask` and then do a `cmix`. Applications that want `cmov` for constant execution time for security reasons can cope with it using a couple of extra instructions. Applications that want `cmov` for average performance because the condition is unpredictable are mostly mistaken with modern branch prediction :-) There is a fairly strong possibility that a pair of instructions might be added to put `cmov` emulation on the same footing as `cmix`: Rd = Rs2 ? Rs1 : 0 Rd = Rs2 ? 0 : Rs1 These instructions only need two register inputs.
- panick21_ 4y agoYou are right, it was removed and is no longer in the newer spec: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...