It's Chisel < https://www.chisel-lang.org/ https://www.chisel-lang.org/ > which runs on Scala and generates synthesizable Verilog for hardware implementation.

It's Chisel < https://www.chisel-lang.org/ https://www.chisel-lang.org/ > which runs on Scala and generates synthesizable Verilog for hardware implementation. It was created and used by the same group that created RISC-V so it makes perfect sense. SiFive, arguably the biggest player in RISC-V, use Chisel to design their processors.