It's not magic. Slower but cheaper than SRAM cells, DRAM-derived logic needs to refresh periodically and partially/fully when read. It's likely an inability to

It's not magic. Slower but cheaper than SRAM cells, DRAM-derived logic needs to refresh periodically and partially/fully when read. It's likely an inability to model worst-case current needs or clocking accurately enough to match reality when a large number of cells reinforce a draining property.