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ARM has two main architectures right now: 32-bit v7 and 32/64-bit v8-9. They sometimes run compressed ISA (eg thumb2) but that is still part of thr same archite

ARM has two main architectures right now: 32-bit v7 and 32/64-bit v8-9. They sometimes run compressed ISA (eg thumb2) but that is still part of thr same architecture. I don't know what the blobs you mention have to do with this RISC-V despite its young age is even more fragmented. This is because the Berkeley folks took their sweet time to finish important parts of the spec and in in the mean time multiple companies shiped out RISCV with home grown ISA changes.

panick21_ 4y ago
There was no realistic chance of Berkeley to 'finish' the spec. The specs were finished in the foundation not just by Berkeley. Fragmentation is a feature of RISC-V, and often it represents actual diversity in use, more then just needless fragmentation. And the majority of the time its additions, not changes to anything that in the spec. And RISC-V specifies how that it is be done in order to stay compatible. In terms of software for Linux its not actually fragmented. Pretty much all major linux and free software distribution agree on targeting the RV-A profiles.
- kramerger 4y ago
  When was the base instruction set published? When was the privileged ISA finalised? How many CPUs with a home grown memory protection designs were sold between those two dates? Please don't confuse this with openness
  - brucehoult 4y ago
    2015 and July 2019, though the HiFive Unleashed shown in late 2017 and shipped in February or March 2018 ended up being compatible with the privileged ISA ratified in 2019. > How many CPUs with a home grown memory protection designs were sold between those two dates? Zero that I'm aware of. Want to inform us? The Canaan Kendryte K210 dual core 400 MHz 64 bit microcontroller shipped with an incompatible MMU, but it wasn't home grown — it's unmodified Berkeley Rocket implementing the current version (Priv 1.9.1) as at the time Canaan took the core snapshot for their SoC. If that chip was a serious Linux target then priv 1.9.1 support could be put BACK in the Linux kernel (it wasn't upstreamed but it existed and was published). But with only 8 MB of non-expandable on chip SRAM there is no point anyway.

panick21_ 4y ago

There was no realistic chance of Berkeley to 'finish' the spec. The specs were finished in the foundation not just by Berkeley. Fragmentation is a feature of RISC-V, and often it represents actual diversity in use, more then just needless fragmentation. And the majority of the time its additions, not changes to anything that in the spec. And RISC-V specifies how that it is be done in order to stay compatible. In terms of software for Linux its not actually fragmented. Pretty much all major linux and free software distribution agree on targeting the RV-A profiles.

kramerger 4y ago
When was the base instruction set published? When was the privileged ISA finalised? How many CPUs with a home grown memory protection designs were sold between those two dates? Please don't confuse this with openness
- brucehoult 4y ago
  2015 and July 2019, though the HiFive Unleashed shown in late 2017 and shipped in February or March 2018 ended up being compatible with the privileged ISA ratified in 2019. > How many CPUs with a home grown memory protection designs were sold between those two dates? Zero that I'm aware of. Want to inform us? The Canaan Kendryte K210 dual core 400 MHz 64 bit microcontroller shipped with an incompatible MMU, but it wasn't home grown — it's unmodified Berkeley Rocket implementing the current version (Priv 1.9.1) as at the time Canaan took the core snapshot for their SoC. If that chip was a serious Linux target then priv 1.9.1 support could be put BACK in the Linux kernel (it wasn't upstreamed but it existed and was published). But with only 8 MB of non-expandable on chip SRAM there is no point anyway.