3 ms·

isn't that why RISC exists?

shash 4y ago
You mean RISC-V I suppose? It doesn’t _exist_ because of this, but it’s definitely getting a lot of attention because of this.
- hulitu 4y ago
  ARM is a mess as an architecture ( every ARM has different ISA, you need blobs for the majority of it to make it work and OS support is lacking). RISC-V is almost nonexistent (where can i buy one at a reasonable price? ) and it seems that it has the same fragmentation problem.
  - brucehoult 4y ago
    >RISC-V is almost nonexistent Over 10 billion shipped so far. Chances are you're using a few without realising it. Got an Android phone made since 2019? Qualcomm has shipped 650 million Snapdragon SoCs with RISC-V in them. Got a WD hard drive? Got an NVidia GPU made in the last five years or so? > where can i buy one at a reasonable price? What are you after, exactly? 50 chips for $5? https://www.aliexpress.us/item/1005005036714708.html https://www.aliexpress.us/item/1005005036714708.html A quad core 1.5 GHz Linux SBC at near Raspberry Pi price? https://www.amazon.com/youyeetoo-StarFive-VisionFive2-Computer-Version/dp/B0BQJ1K9VK https://www.amazon.com/youyeetoo-StarFive-VisionFive2-Comput... Those are the extremes of the mainstream range you can buy right now. Considerably higher performance is rolling out all year, including many-core (e.g. 64) OoO server chips.
  - piperswe 4y ago
    In fact, one of the main reasons for RISC-V's existence is fragmentation - the ISA is meant to be extended and not meant to be one-size-fits-all. The core of the ISA is designed for everything from microcontrollers to supercomputers, but extensions tend to fall closer to one side of that.
    - shash 4y ago
      Or, an other way to put it is, it’s an attempt to build diversity without fragmentation. The spec follows the open closed principle in a sense - it’s open for extension but closed for modification, and if you choose to target say RV64G, you know that it will run on most 64 bit RISC-V processors. If you choose an extension, it’s not all that different from, say, figuring out which of Intel’s various SSE extensions is actually available. Of course, there are vendors who are only RISC-V adjacent, but they will either put up, shut up or subsume the entire ecosystem if they get big enough. Time will tell.
  - kramerger 4y ago
    ARM has two main architectures right now: 32-bit v7 and 32/64-bit v8-9. They sometimes run compressed ISA (eg thumb2) but that is still part of thr same architecture. I don't know what the blobs you mention have to do with this RISC-V despite its young age is even more fragmented. This is because the Berkeley folks took their sweet time to finish important parts of the spec and in in the mean time multiple companies shiped out RISCV with home grown ISA changes.
    - panick21_ 4y ago
      There was no realistic chance of Berkeley to 'finish' the spec. The specs were finished in the foundation not just by Berkeley. Fragmentation is a feature of RISC-V, and often it represents actual diversity in use, more then just needless fragmentation. And the majority of the time its additions, not changes to anything that in the spec. And RISC-V specifies how that it is be done in order to stay compatible. In terms of software for Linux its not actually fragmented. Pretty much all major linux and free software distribution agree on targeting the RV-A profiles.
      - kramerger 4y ago
        When was the base instruction set published? When was the privileged ISA finalised? How many CPUs with a home grown memory protection designs were sold between those two dates? Please don't confuse this with openness
        brucehoult 4y ago
        2015 and July 2019, though the HiFive Unleashed shown in late 2017 and shipped in February or March 2018 ended up being compatible with the privileged ISA ratified in 2019. > How many CPUs with a home grown memory protection designs were sold between those two dates? Zero that I'm aware of. Want to inform us? The Canaan Kendryte K210 dual core 400 MHz 64 bit microcontroller shipped with an incompatible MMU, but it wasn't home grown — it's unmodified Berkeley Rocket implementing the current version (Priv 1.9.1) as at the time Canaan took the core snapshot for their SoC. If that chip was a serious Linux target then priv 1.9.1 support could be put BACK in the Linux kernel (it wasn't upstreamed but it existed and was published). But with only 8 MB of non-expandable on chip SRAM there is no point anyway.

You mean RISC-V I suppose? It doesn’t _exist_ because of this, but it’s definitely getting a lot of attention because of this.

hulitu 4y ago
ARM is a mess as an architecture ( every ARM has different ISA, you need blobs for the majority of it to make it work and OS support is lacking). RISC-V is almost nonexistent (where can i buy one at a reasonable price? ) and it seems that it has the same fragmentation problem.
- brucehoult 4y ago
  >RISC-V is almost nonexistent Over 10 billion shipped so far. Chances are you're using a few without realising it. Got an Android phone made since 2019? Qualcomm has shipped 650 million Snapdragon SoCs with RISC-V in them. Got a WD hard drive? Got an NVidia GPU made in the last five years or so? > where can i buy one at a reasonable price? What are you after, exactly? 50 chips for $5? https://www.aliexpress.us/item/1005005036714708.html https://www.aliexpress.us/item/1005005036714708.html A quad core 1.5 GHz Linux SBC at near Raspberry Pi price? https://www.amazon.com/youyeetoo-StarFive-VisionFive2-Computer-Version/dp/B0BQJ1K9VK https://www.amazon.com/youyeetoo-StarFive-VisionFive2-Comput... Those are the extremes of the mainstream range you can buy right now. Considerably higher performance is rolling out all year, including many-core (e.g. 64) OoO server chips.
- piperswe 4y ago
  In fact, one of the main reasons for RISC-V's existence is fragmentation - the ISA is meant to be extended and not meant to be one-size-fits-all. The core of the ISA is designed for everything from microcontrollers to supercomputers, but extensions tend to fall closer to one side of that.
  - shash 4y ago
    Or, an other way to put it is, it’s an attempt to build diversity without fragmentation. The spec follows the open closed principle in a sense - it’s open for extension but closed for modification, and if you choose to target say RV64G, you know that it will run on most 64 bit RISC-V processors. If you choose an extension, it’s not all that different from, say, figuring out which of Intel’s various SSE extensions is actually available. Of course, there are vendors who are only RISC-V adjacent, but they will either put up, shut up or subsume the entire ecosystem if they get big enough. Time will tell.
- kramerger 4y ago
  ARM has two main architectures right now: 32-bit v7 and 32/64-bit v8-9. They sometimes run compressed ISA (eg thumb2) but that is still part of thr same architecture. I don't know what the blobs you mention have to do with this RISC-V despite its young age is even more fragmented. This is because the Berkeley folks took their sweet time to finish important parts of the spec and in in the mean time multiple companies shiped out RISCV with home grown ISA changes.
  - panick21_ 4y ago
    There was no realistic chance of Berkeley to 'finish' the spec. The specs were finished in the foundation not just by Berkeley. Fragmentation is a feature of RISC-V, and often it represents actual diversity in use, more then just needless fragmentation. And the majority of the time its additions, not changes to anything that in the spec. And RISC-V specifies how that it is be done in order to stay compatible. In terms of software for Linux its not actually fragmented. Pretty much all major linux and free software distribution agree on targeting the RV-A profiles.
    - kramerger 4y ago
      When was the base instruction set published? When was the privileged ISA finalised? How many CPUs with a home grown memory protection designs were sold between those two dates? Please don't confuse this with openness
      - brucehoult 4y ago
        2015 and July 2019, though the HiFive Unleashed shown in late 2017 and shipped in February or March 2018 ended up being compatible with the privileged ISA ratified in 2019. > How many CPUs with a home grown memory protection designs were sold between those two dates? Zero that I'm aware of. Want to inform us? The Canaan Kendryte K210 dual core 400 MHz 64 bit microcontroller shipped with an incompatible MMU, but it wasn't home grown — it's unmodified Berkeley Rocket implementing the current version (Priv 1.9.1) as at the time Canaan took the core snapshot for their SoC. If that chip was a serious Linux target then priv 1.9.1 support could be put BACK in the Linux kernel (it wasn't upstreamed but it existed and was published). But with only 8 MB of non-expandable on chip SRAM there is no point anyway.