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I don't know what you're even talking about here. Intel's "Horse Creek" RISC-V SoC is build on Intel 4, which is a "vaguely recent node". So recent, it's the f
by brucehoult 4y ago
I don't know what you're even talking about here.
Intel's "Horse Creek" RISC-V SoC is build on Intel 4, which is a "vaguely recent node". So recent, it's the first chip made using it. You'll be able to buy a board using those around August or so. Working chips were shown at a conference last September.
Ventana's "Veyron 1" RISC-V SoC uses either TSMC 5nm or 3nm. Those are also "vaguely recent". That's an 8-wide 3.6 GHz core, btw, like Apple M1/M2, well ahead of Intel, AMD, or ARM itself.
As for "Power management, coherency fabric, there's so many other things mobile chips are great at, tuned at", if you are someone who already has such as chip, such as oh I don't know Qualcomm or Samsung or for that matter Rockchip or Allwinner, and you already have ARM-based chips with all that stuff, and you swap out the ARM cores for RISC-V cores -- then you still have all that non-core stuff.
- rektide 4y agoBelieve me I'd be happy to be wrong. Thusfar there don't seem to be any generally available chips in the world. No one has benchmarked anything modern. We don't know what to expect yet, there are no known quantities, from what I can tell. I'd forgotten about Horse Creek. It's certainly an interesting future board. I like that it has 10Gbe and some USB3. And PCIe 5.0! That does look modern. Not expecting a high value, a good price, but this could be a good starting place & we should learn! I kind of though Intel had canceled all their RISC-V stuff, but this SiFive board is likely unaffected. However the rest of their once ambitious RISC-V foundry assistance program seems to have been recently killed off, that's why I (accidentally) ruled them out. https://www.theregister.com/2023/01/30/intel_ris_v_pathfinder_discontinued/ https://www.theregister.com/2023/01/30/intel_ris_v_pathfinde... I think the vast majority of the chips out there use ARMs CoreLink and Cache Connect Interface. There's a ton of platform, tuning & fabric that I still suspect is missing from most chipmaking orgs, that's going to require intense redevelopment & which will take lots of release iterations to become decent. Ventana is a good mention. They don't seem to be shipping at the moment, don't seem to have anyone posting benchmarks on chips they have. Still to me an unknown quantity, but yeah totally as modern a process as we can expect, very exciting.
- brucehoult 4y agoIntel killed an IDE that was redundant with other existing IDEs. Nothing at all to do with Horse Creek or Intel Foundry Services as a chip-making service. No one is shipping really high performance RISC-V yet because it takes 3 or 4 years from project start to having working silicon and it is less than four years since the initial RV{32,64}GC ISAs were frozen and ratified in July 2019. Lots more stuff extremely important for mobile to servers to supercomputers was ratified in November 2021, including the Vector ISA, cache control instructions, hypervisor spec, bit manipulation instructions (clz, popcount and things like that), 16 bit FP, crypto in scalar registers (SHA, AES), PAUSE instruction, page-based physical memory attributes (e.g. cacheable or not). That's less than a year and a half ago. Cores and chips are in the pipeline, being made by credible people who WILL make what they say they will, but it all takes time. Meantime, the THead C910 core -- first announced in July 2019 -- which is roughly equivalent to the ARM A73 or A73 was available (as usually happens) on an expensive dev board in late 2021 and is coming out in quad core 2.5 GHz form on a $99 board in April (probably). SOPHGO have recently shown a board with the SG2042 chip with 64 C910 cores running at 2.0 GHz. I expect to have access to one of these boards shortly. Of course these boards, using cores designed in 2019, use the RISC-V specs that were available in 2019, including an early draft (0.7.1) version of the Vector extension which is very similar to but incompatible with the eventual 1.0 ratified in November 2021. Not completely incompatible -- common byte-oriented functions such as memcpy, memcmp, strlen, strcpy, strcmp etc are binary compatible between 0.7.1 and 1.0, and most other things are easy, trivial, modifications. Much much easier than converting between AVX and NEON or between SVE and RISC-V V. Expect expensive low production volume chips and boards with RVV 1.0 next year, and cheap mass production ones in 2026. That's how the chip industry rolls. There is a very long production process. But these things are in the pipeline, they are coming, we know what they will do when they get here, and there is virtually zero chance that they won't eventuate.
- rektide 4y agoI like your use of time-scales to try to explain why we are where we are. I hope very much you're right that what we see now is isn't really reflective. That a ton of really big improvements to RISC-V cores are being lined up, will show up. I'm not going to judge too quickly. But man, waiting till 2026 feels hard. Whether we have any intermittent experience of RISC-V closing the gap in that time is still in doubt to me. And I keep worrying that we'll forever see a huge split: a bunch of super cheap super low-end RISC-V application-processors that are just not good, and a bunch of many-thousand-dollar fancy units, that may or may not get actually good benchmarks/availability. With ARM potentially getting absurd & stupid, the good value for a sub $100 or sub $300 SBC seems like the real competition, and I just have such concern RISC-V is going to bifuracte between extremely up-market & extremely cheap crap.