Oh that is really cool! Way back in my undergrad I worked on a tiny tiny part of the insertable B layer, writing some very bad FPGA firmware to control the T3MA

Oh that is really cool! Way back in my undergrad I worked on a tiny tiny part of the insertable B layer, writing some very bad FPGA firmware to control the T3MAPS test chip (I think this was for Phase 2 upgrades?). FPGAs everywhere in this domain! And yeah the detectors are arranged in a really complicated way, I can imagine that is a hide headache.