It probably already does that. It probably goes even further. Intel CPUs since the Core uarch have a stack engine. This basically does the addition or subtract

It probably already does that. It probably goes even further. Intel CPUs since the Core uarch have a stack engine. This basically does the addition or subtraction of the stack pointer in a special piece of hardware straight after the decode stage. It can also do this multiple times per clock. The result after decode is that each PUSH/POP/PUSHQ/POPQ will decode down to a single uop. Combined with multiple decoding pipes and a superscaler load/store unit the CPU basically packs a stream of PUSH(Q)/POP(Q) instructions into a tight little ball of uops which are executed at lightning speed. On Alder Lake for instance it can do 3 loads and 4 stores per clock. This is also faster than putting an instruction like PUSHA/POPA through a uarch decoder so nobody uses those instructions anymore. They're not even available in the x64 ISA. As shown, modern CPUs are so good at decoding a stream of individual PUSH(Q)/POP(Q) instructions there's literally no point.