3 ms·
> The ISA spec includes commentary on this decision (page 23), noting some disadvantages of adding such instructions to the specification and noting microarchit
by andrekandre 4y ago
> The ISA spec includes commentary on this decision (page 23), noting some disadvantages of adding such instructions to the specification and noting microarchitectural techniques exist to convert short forward branches into predicated code internally. In the case of the SiFive 7 series, this is achieved using macro-op fusion where a branch over a single ALU instruction is fused and executed as a single conditional instruction.
i wonder how far can macro-op fusion be taken?
would it be possible to implement something like push/pop all registers where the hardware decoder gobbles up several consecutive load (or store) instructions and executes an (accelerated) batch under the covers?
(maybe thats a trick they already do i suppose....)
- Veliladon 4y agoIt probably already does that. It probably goes even further. Intel CPUs since the Core uarch have a stack engine. This basically does the addition or subtraction of the stack pointer in a special piece of hardware straight after the decode stage. It can also do this multiple times per clock. The result after decode is that each PUSH/POP/PUSHQ/POPQ will decode down to a single uop. Combined with multiple decoding pipes and a superscaler load/store unit the CPU basically packs a stream of PUSH(Q)/POP(Q) instructions into a tight little ball of uops which are executed at lightning speed. On Alder Lake for instance it can do 3 loads and 4 stores per clock. This is also faster than putting an instruction like PUSHA/POPA through a uarch decoder so nobody uses those instructions anymore. They're not even available in the x64 ISA. As shown, modern CPUs are so good at decoding a stream of individual PUSH(Q)/POP(Q) instructions there's literally no point.
- deleted 4y ago[deleted]