4 ms·

I don't understand the significance of this. Tried to read up on what PHY refers to, but didn't connect the dots. How will this make progress?

matthews2 4y ago
The PHY (physical layer) turns the boring digital signals from our microcontroller into exciting analogue/RF signals.
mschuster91 4y ago
an Ethernet PHY layer usually refers to the layer that makes digital signals suitable for transmission on the medium (and the inverse for receiving). Think for example a standard SoC chip for an embedded device scenario - it will have one or more MII ports [1]. Onto these MII ports, you can then attach a PHY chip for your needs... Ethernet, coax, fiber optics, direct connection, whatever, so you don't need to change your SoC chip or even your operating system just if you want to offer a product with Ethernet and fiber networking. Usually, these chips are proprietary... but this project provides an open source implementation, so that in the worst case of no one producing Ethernet PHYs any more, you can take an FPGA instead. [1] https://en.wikipedia.org/wiki/Media-independent_interface https://en.wikipedia.org/wiki/Media-independent_interface
- chrisMyzel 4y ago
  could someone please break this down even more :) I can make a 100 Gbit repeater using an FPGA with this?
  - mschuster91 4y ago
    No. 100BASE is 100 mbit/s.
  - stephen_g 4y ago
    100Gbps requires expensive FPGAs because you need very fast SERDES peripherals on-die to transmit/receive the four lanes of 25Gbps to the other device (usually a QSFP28 module but you can communicate directly between two chips with just SERDES without converting to any kind of Ethernet). Normal logic pins on FPGAs generally can’t be used to transmit or receive fast enough (not to mention some of these standards are using multi-level signalling like PAM-4 which a normal logic pin just can’t do). 100Mbps on the other hand (like this project is doing) is possible to produce, but I do wonder how likely it would be to be able to practically receive with any meaningful cable length without an analogue front-end that you find in a PHY.
    - nrclark 4y ago
      This core is 100BASE-X, not 100BASE-T. It's intended to run over fiber, presumably using SFP modules.
      - stephen_g 4y ago
        It seems to have modules for both.
- gnu8 4y ago
  Has anyone ever seen an interface that plugs into the MII port pictured in that article? I had a Sun machine with that connector but I never had an adapter for it. There was also a normal RJ45 jack so I didn’t need one but I was always curious.

matthews2 4y ago

The PHY (physical layer) turns the boring digital signals from our microcontroller into exciting analogue/RF signals.

mschuster91 4y ago

an Ethernet PHY layer usually refers to the layer that makes digital signals suitable for transmission on the medium (and the inverse for receiving). Think for example a standard SoC chip for an embedded device scenario - it will have one or more MII ports [1]. Onto these MII ports, you can then attach a PHY chip for your needs... Ethernet, coax, fiber optics, direct connection, whatever, so you don't need to change your SoC chip or even your operating system just if you want to offer a product with Ethernet and fiber networking. Usually, these chips are proprietary... but this project provides an open source implementation, so that in the worst case of no one producing Ethernet PHYs any more, you can take an FPGA instead. [1] https://en.wikipedia.org/wiki/Media-independent_interface https://en.wikipedia.org/wiki/Media-independent_interface

chrisMyzel 4y ago
could someone please break this down even more :) I can make a 100 Gbit repeater using an FPGA with this?
- mschuster91 4y ago
  No. 100BASE is 100 mbit/s.
- stephen_g 4y ago
  100Gbps requires expensive FPGAs because you need very fast SERDES peripherals on-die to transmit/receive the four lanes of 25Gbps to the other device (usually a QSFP28 module but you can communicate directly between two chips with just SERDES without converting to any kind of Ethernet). Normal logic pins on FPGAs generally can’t be used to transmit or receive fast enough (not to mention some of these standards are using multi-level signalling like PAM-4 which a normal logic pin just can’t do). 100Mbps on the other hand (like this project is doing) is possible to produce, but I do wonder how likely it would be to be able to practically receive with any meaningful cable length without an analogue front-end that you find in a PHY.
  - nrclark 4y ago
    This core is 100BASE-X, not 100BASE-T. It's intended to run over fiber, presumably using SFP modules.
    - stephen_g 4y ago
      It seems to have modules for both.
gnu8 4y ago
Has anyone ever seen an interface that plugs into the MII port pictured in that article? I had a Sun machine with that connector but I never had an adapter for it. There was also a normal RJ45 jack so I didn’t need one but I was always curious.