4 ms·

Really? Not sure why. MIPS had multiply and divide instructions; ARM had multiply instructions; I know SH-4 has at least multiply instructions. I don't think

Really? Not sure why. MIPS had multiply and divide instructions; ARM had multiply instructions; I know SH-4 has at least multiply instructions. I don't think hardware multiplication is a RISC or CISC thing. The "reduced instructions" that RISC is concerned with chiefly involve code flow mechanisms such as linkage, flag behavior, and interfacing with memory. It doesn't mean you need to create all your math operations from increment and bitwise instructions. The RISC/CISC thing stopped being meaningful once ... A) processors went all-in on out-of-order execution (this means everything was split into uops and reordered and your instruction stream no longer represents what the CPU does much of the time) B) processors started having parallel vector instructions. An article was posted here on HN making the case for considering "Out of Order" a new paradigm and it made a lot of sense to me.

garganzol 4y ago
RISC crowd presented lower number of transistors as one of the top selling points back in the day. Simpler instructions => fewer transistors => less heat => more room for performance, at least on paper. MUL and DIV instructions are not exactly transistor count friendly, so they caused an expected contradiction at the RISC camp back in the day.
- rst 4y ago
  Some first-generation RISC processors, e.g. MIPS R2000, shipped with hardware multiply and divide, or even optional floating point.
eru 4y ago
> A) processors went all-in on out-of-order execution (this means everything was split into uops and reordered and your instruction stream no longer represents what the CPU does much of the time) Yes. That's why it has become more and more ridiculous to claim that C is 'close to the metal'.