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You're comparing a 5W CPU to an entire SoM that only draws 2W. Just making that switch cuts battery life to a little over an hour in this device. You're also
by stonogo 4y ago
You're comparing a 5W CPU to an entire SoM that only draws 2W. Just making that switch cuts battery life to a little over an hour in this device.
You're also comparing a SiFive product whose documentation is mostly "this document will be updated soon" to a product that comes with complete schematics and all the documentation you could ask for.
I don't think you understand the design considerations at play here.
- snvzz 4y ago>You're comparing a 5W CPU to an entire SoM that only draws 2W. JH7110 is not a CPU, but a fully featured SoC. The power consumption is like: >In sleep mode, the static power consumption of JH7110 is 120 mW. When working on an SBC, with all the main modules under full load, the dynamic power consumption of JH7110 is 4,100 mW. Source: https://www.design-reuse.com/news/52544/starfive-risc-v-jh7110-soc-visionfive-2-sbc.html https://www.design-reuse.com/news/52544/starfive-risc-v-jh71...
- stonogo 4y agoGranted. So power consumption is "only" doubled from the existing product and runtime is "only" cut in half. The benefit is that the project is now harder to execute and the BOM is more expensive, assuming you can get through the lack of documentation. It's still a bad fit.
- snvzz 4y agoWe'd need to know what the actual load is with both chips. That 4.1w figure is a maximum, using all the SoC's modules, at the spec clock. To put in perspective, the NXP's SoC 2.1w figure is just for the CPU[0]. 0. https://www.nxp.com/docs/en/fact-sheet/IMX8MPLUSFS.pdf https://www.nxp.com/docs/en/fact-sheet/IMX8MPLUSFS.pdf