4 ms·
Of course they are free to add new "more powerful" instructions to SVE at any time, just like Intel could for AVX, etc. Also, I think it is supposed to be easi
by evancox100 4y ago
Of course they are free to add new "more powerful" instructions to SVE at any time, just like Intel could for AVX, etc.
Also, I think it is supposed to be easier for compilers to autovectorize SVE than, say, neon. Whether that's the case in practice I don't know. Is there something specific you see that makes it more difficult than with SIMD-style, fixed operation width instructions? Or you are referring to something else with "compiler support"?