4 ms·
No, but they're a useful target for Verilog, and this limitation is shared by any hardware compute/circuit (I had hoped that would be obvious from the descripti
by geocar 4y ago
No, but they're a useful target for Verilog, and this limitation is shared by any hardware compute/circuit (I had hoped that would be obvious from the description)
- skissane 4y agoYou can implement a CPU completely with random logic, zero microcode - it has been done before. Yes you do end up needing something like extra registers to hold control state - but that’s not microcode