Yeah. If you've ever had to deal with metastability and eyes in digital signals, you'd know that "digital" is frequently less 0 and 1 than we normally think ab

Yeah. If you've ever had to deal with metastability and eyes in digital signals, you'd know that "digital" is frequently less 0 and 1 than we normally think about. There's a reason you can't just take a System Verilog FPGA and make an ASIC out of it that will work on the first time, and that there are entire teams and libraries to do it. And they'll still get things wrong that need to be fixed after they're discovered. edit: the only reason we can blissfully ignore the underlying analog world is through the unceasing effort of asic designers, analog engineers, verification teams, firmware teams, and as a last line of defense, some poor bastard writing the driver to work around something that can't be fixed with any other method.