RISC is about pipelining more than ISA, really. Yes, these are tiny instructions, but the CPU is doing only one of them at a time. In a RISC core[1], the CPU

RISC is about pipelining more than ISA, really. Yes, these are tiny instructions, but the CPU is doing only one of them at a time. In a RISC core[1], the CPU would be fetching an instruction from address X, while the instruction at address X-4 (fetched last cycle) was being presented to the decoder, at the time time the decoded instruction from X-8 was being presented to the ALU for execution (or FPU, or load/store unit, etc...), at the same time the instruction at X-12's result was being written back into the register file. You still get only one instruction per cycle[2], but the circuit depth is lower and you can run faster. The tradeoff is that you need enough hardware on the chip to do all this at one time. The microcode solution can share resources between different instructions because they don't operate at the same time. [1] This is more or less the original four-stage RISC setup. Modern CPUs have many more pipeline stages, including handling for things like L1 cache. [2] Superscalar CPUs extend this idea by having multiple execution pipelines running in parallel, fed by an instruction fetch/decode unit that can figure out and emit more than one instruction in a cycle.