2 ms·
What a wacky lovely board. A wild plan: use a NVMe controller, but use FPGAs to translate & interface with DDR3 ram. It definitely foreshadows what CXL is goin
by rektide 4y ago
What a wacky lovely board. A wild plan: use a NVMe controller, but use FPGAs to translate & interface with DDR3 ram.
It definitely foreshadows what CXL is going for!