well, for example in ARMv7 and below, it was common to use LR(r14) ALSO for math during the function body if there was register pressure. So it does assist a li

well, for example in ARMv7 and below, it was common to use LR(r14) ALSO for math during the function body if there was register pressure. So it does assist a little. And the instruction set encoding is much simpler if every reg is just ... a reg. No need for push and pop if you can store with predecrement and load with postincrement. And those stores/loads are useful ALSO for non-stack ops, if your compiler is clever. _At the time_ the design made good sense. But in modern very-OoO cpus, you are right, and having SP and PC be GPRs is of little use and of non-negilible cost design-wise, which is why in aarch64, SP and PC are special and not GPRs like they were in ARMv7 and below. LR still is a GPR though