That's just the start of it. On Arm you also have the secure state and exception level. Non-Secure EL0 is user space, with limited access to system register

That's just the start of it. On Arm you also have the secure state and exception level. Non-Secure EL0 is user space, with limited access to system registers. Non-Secure EL1 is kernel space with more access to system registers. Non-Secure EL2 is hypervisor space with more access to system registers. EL3 is the secure monitor. I'm not sure what the secure states ELs can do, or if they have the same 3 ELs available as the non-secure side. Likely not. I've never used them, but I think the secure state is described as though intended for a set of micro-services that the Non-Secure levels can send requests to. There are extensions allowing Hypervisor EL2 to be a Secure state. A secure hypervisor may be able to manage secure and non-secure kernels. Arm allow various levels to not be implemented, supporting weird combos, like EL2 and EL0, without an EL1. The current state can also control what you're allowed to do with peripherals, like the interrupt controller. Even if provided access to the GIC's full register set, code running in a non-secure state cannot reconfigure or induce a secure interrupt. Any such requests will be ignored. Secure and non-secure accesses to memory may read from entirely different RAM chips. ...The execution state gets kinda complicated.