It’s in large part due to the wire density… a 6T SRAM bit cell by itself could scale transistor density well, but the word lines and bit lines are the limiters

It’s in large part due to the wire density… a 6T SRAM bit cell by itself could scale transistor density well, but the word lines and bit lines are the limiters as they typically have to go up 4 metal layers. Also, each read/write port you add to the SRAM macro increases the size exponentially rather than the linear scaling of the bit cells.