3 ms·
Even the density figures are mostly lies. For example TSMCs N5 is closer to 134MTr/mm2 in the real world[1]. It can also depend on the chip design itself. Some
by thunderbird120 4y ago
Even the density figures are mostly lies. For example TSMCs N5 is closer to 134MTr/mm2 in the real world[1]. It can also depend on the chip design itself. Some designs may scale better than others because not all transistors get the same density improvement from new nodes. Ultimately simple metrics for predicting performance are sort of breaking down at the scale these chips are currently being manufactured at. For example, their TSMCs N3 increases transistor density for logic transistors but SRAM sees no improvement over N5[2].
[1]https://www.angstronomics.com/p/the-truth-of-tsmc-5nm https://www.angstronomics.com/p/the-truth-of-tsmc-5nm
[2]https://www.tomshardware.com/news/no-sram-scaling-implies-on-more-expensive-cpus-and-gpus https://www.tomshardware.com/news/no-sram-scaling-implies-on...
- eigenform 4y agoIs this some image of how the devices you'd build with SRAM (ie. big uniform array of bitcells) are very regular? I feel like logic being not-as-uniform makes the talk about density scaling different, but I can't exactly articulate how
- trsohmers 4y agoIt’s in large part due to the wire density… a 6T SRAM bit cell by itself could scale transistor density well, but the word lines and bit lines are the limiters as they typically have to go up 4 metal layers. Also, each read/write port you add to the SRAM macro increases the size exponentially rather than the linear scaling of the bit cells.
- eigenform 4y agoI see! Thanks for finishing the thought!