> There are a couple of efficiency reason besides the simple fact that every piece of hardware in existence operates on data sizes in powers of the byte. To st

> There are a couple of efficiency reason besides the simple fact that every piece of hardware in existence operates on data sizes in powers of the byte. To start off with it would be fantastically inefficient to build a cpu that could load arbitrary bit locations so you would either be restricted to loading memory locations that are some reasonable fraction of the internal cache line or pay a massive performance penalty to load a bit address. The Intel iAPX 432 did use bit-aligned instructions: > https://en.wikipedia.org/w/index.php?title=Intel_iAPX_432&oldid=1133519569#Architecture https://en.wikipedia.org/w/index.php?title=Intel_iAPX_432&ol...