3 ms·
Big guess here (I mostly know CPU design from what EE I gleaned from college) but my guess is that the L3 is shared per CCX, which probably makes it harder to p
by to11mtm 4y ago
Big guess here (I mostly know CPU design from what EE I gleaned from college) but my guess is that the L3 is shared per CCX, which probably makes it harder to properly power down/up when only one core is in use.