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ASIC guy here, too. The thing I find most alarming about hardware design is that functional simulation is reaching the end of its useful life because the major

by jgw 15y ago

ASIC guy here, too. The thing I find most alarming about hardware design is that functional simulation is reaching the end of its useful life because the majority of simulators are single-threaded. We're trying to keep up with Moore, and yet our simulation capacity has been plateaued for a few years now. And yet I hear very few ASIC designers and verification engineers complaining about it. We have formal tools, and FPGA prototyping, but by and large, most designs are verified and debugged under one of the big 3 simulators. I think a lot of software guys would be astounded at how backwards the ASIC design community is. To say nothing of the monstrosity that it SystemVerilog.

eric-hu 15y ago
Out of curiosity, how complex are these simulator tools? What sorts of physics and electrical engineering knowledge (in addition to CS knowledge for taking advantage of modern programming techniques) would one require to be able to write a minimum competing product?
- mynegation 15y ago
  Complicated enough to support companies with market cap of $3 Bn ($CDNS) and 1.5 Bn ($MENT) and these are just two leaders.
  - jodrellblank 15y ago
    That doesn't answer the question of a minimum competing product, they could be huge bureacratic cash cows...?
    - deleted 15y ago
      [deleted]
  - deleted 15y ago
    [deleted]
  - jgw 15y ago
    True enough, but as I mentioned in my long ramble, what I'm talking about here are simulators, which make up just a small part of a design suite. (And Synopsys is larger than either Cadence or Mentor, actually)
- zbyszek 15y ago
  I know someone who programs EDA tools and this is what I have observed: You need to know how to make an IC out of lumps of metal, or at least know someone who does. If this were simple they wouldn't pay designers so well (sweeping generalisation based on a sample size of 1). Your real problem, though, is the extremely conservative nature of your potential clients -- understandable when you consider the huge sums at stake in manufacturing, but frustrating nonetheless. If you can create a tool that works exactly like an existing one did in the olden days, then they might be interested. If you use "modern programming techniques" for goodness sake keep stumm about it.
- jgw 15y ago
  To be clear, I'm specifically talking about Verilog simulators here. The EDA industry produces a wide range of tools for doing simulation, timing analysis, synthesis (converting a design to a gate-level netlist), DFT (automatic insertion of in-silicon testing facilities), layout, routing, analog design, and so on. You need a lot of tools to get a chip from your brain to a fab. A simulator for doing functional design is just one piece of the puzzle, but it's the one I'm most familiar with. I swear at one every day. To write a digital logic simulator is actually not very difficult at all. I've implemented a sketch of a simple one myself; I'm sure there are some folks here who, if they understood some digital design principles, could write something that would put my humble attempt to shame. But the industry doesn't want a simulator - it wants a Verilog simulator. That such a thing even exists is fundamentally wrong to my mind - a simulator should simulate the function described, not the implementation of said thing in a specific language. My own toy simulator was really a language-agnostic simulation library that you could just link to. Kind of like what SystemC is. But even polished up, I don't see there being any market for such a thing. Most designers don't think there's anything wrong with Verilog, because they don't know anything else, and most verification engineers are delighted to be using SystemVerilog because it makes us feel like we're on the cutting edge of technology for using a language that looks like a severely crippled Java, rather than one that looks like a regular crippled C. Many would not understand the previous sentence. Ironically, Verilog doesn't really lend itself to parallelization very well. The language was not designed with that in mind, if it was "designed" at all. So single-threaded seems the way to go, and that space is already too crowded. There are a couple of multi-threaded Verilog simulators out there, but they're not widely used, and I suspect the performance is not all that great, because of the semantics of the language. There have been attempts to push new languages. One, called Bluespec, is a Haskell front end to SystemVerilog, but doesn't seem to get much traction, as far as I can tell. And even if it did, the demographics of our industry would be a problem. I'm not sure how many of us could handily pick up Haskell. So it seems we're stuck with Verilog, and Verilog really is a problem. Hats off to Phil Moorby for coming up with a language that designers could write some code that looks a bit like C, and have it synthesize to a bunch of equivalent gates. It was a damn cool hack in the 1980s, when it came out, but it's really not a great language, and attempts to bolt on higher-level features on the side (SystemVerilog) just emphasize, in my mind, just how flawed the foundation really is. Our little industry is becoming more and more like software every year, but our demographics are such that we just don't have the pool of really brilliant people driving innovation. I believe I'm generally considered to be a pretty good verification engineer, but I think if I were thrown into a modern software development team, I'd probably struggle to keep up (at least at first). As for the "leaders" in my industry, I know many of them personally, and while they're certainly very intelligent, not one could be compared to luminaries of the software industry. So even amongst our leadership, I sense very little concern that something is seriously wrong. Some get darn right defensive about it. And worse, they seem to have a vested interest in maintaining the status quo. And now I has a sad.

by jgw 15y ago

eric-hu 15y ago

Out of curiosity, how complex are these simulator tools? What sorts of physics and electrical engineering knowledge (in addition to CS knowledge for taking advantage of modern programming techniques) would one require to be able to write a minimum competing product?

mynegation 15y ago
Complicated enough to support companies with market cap of $3 Bn ($CDNS) and 1.5 Bn ($MENT) and these are just two leaders.
- jodrellblank 15y ago
  That doesn't answer the question of a minimum competing product, they could be huge bureacratic cash cows...?
  - deleted 15y ago
    [deleted]
- deleted 15y ago
  [deleted]
- jgw 15y ago
  True enough, but as I mentioned in my long ramble, what I'm talking about here are simulators, which make up just a small part of a design suite. (And Synopsys is larger than either Cadence or Mentor, actually)
zbyszek 15y ago
I know someone who programs EDA tools and this is what I have observed: You need to know how to make an IC out of lumps of metal, or at least know someone who does. If this were simple they wouldn't pay designers so well (sweeping generalisation based on a sample size of 1). Your real problem, though, is the extremely conservative nature of your potential clients -- understandable when you consider the huge sums at stake in manufacturing, but frustrating nonetheless. If you can create a tool that works exactly like an existing one did in the olden days, then they might be interested. If you use "modern programming techniques" for goodness sake keep stumm about it.
jgw 15y ago
To be clear, I'm specifically talking about Verilog simulators here. The EDA industry produces a wide range of tools for doing simulation, timing analysis, synthesis (converting a design to a gate-level netlist), DFT (automatic insertion of in-silicon testing facilities), layout, routing, analog design, and so on. You need a lot of tools to get a chip from your brain to a fab. A simulator for doing functional design is just one piece of the puzzle, but it's the one I'm most familiar with. I swear at one every day. To write a digital logic simulator is actually not very difficult at all. I've implemented a sketch of a simple one myself; I'm sure there are some folks here who, if they understood some digital design principles, could write something that would put my humble attempt to shame. But the industry doesn't want a simulator - it wants a Verilog simulator. That such a thing even exists is fundamentally wrong to my mind - a simulator should simulate the function described, not the implementation of said thing in a specific language. My own toy simulator was really a language-agnostic simulation library that you could just link to. Kind of like what SystemC is. But even polished up, I don't see there being any market for such a thing. Most designers don't think there's anything wrong with Verilog, because they don't know anything else, and most verification engineers are delighted to be using SystemVerilog because it makes us feel like we're on the cutting edge of technology for using a language that looks like a severely crippled Java, rather than one that looks like a regular crippled C. Many would not understand the previous sentence. Ironically, Verilog doesn't really lend itself to parallelization very well. The language was not designed with that in mind, if it was "designed" at all. So single-threaded seems the way to go, and that space is already too crowded. There are a couple of multi-threaded Verilog simulators out there, but they're not widely used, and I suspect the performance is not all that great, because of the semantics of the language. There have been attempts to push new languages. One, called Bluespec, is a Haskell front end to SystemVerilog, but doesn't seem to get much traction, as far as I can tell. And even if it did, the demographics of our industry would be a problem. I'm not sure how many of us could handily pick up Haskell. So it seems we're stuck with Verilog, and Verilog really is a problem. Hats off to Phil Moorby for coming up with a language that designers could write some code that looks a bit like C, and have it synthesize to a bunch of equivalent gates. It was a damn cool hack in the 1980s, when it came out, but it's really not a great language, and attempts to bolt on higher-level features on the side (SystemVerilog) just emphasize, in my mind, just how flawed the foundation really is. Our little industry is becoming more and more like software every year, but our demographics are such that we just don't have the pool of really brilliant people driving innovation. I believe I'm generally considered to be a pretty good verification engineer, but I think if I were thrown into a modern software development team, I'd probably struggle to keep up (at least at first). As for the "leaders" in my industry, I know many of them personally, and while they're certainly very intelligent, not one could be compared to luminaries of the software industry. So even amongst our leadership, I sense very little concern that something is seriously wrong. Some get darn right defensive about it. And worse, they seem to have a vested interest in maintaining the status quo. And now I has a sad.