> According to AMD, MI300 is comprised of 9 5nm chiplets, sitting on top of 4 6nm chiplets. The 5nm chiplets are undoubtedly the compute logic chipets – i.e. th

> According to AMD, MI300 is comprised of 9 5nm chiplets, sitting on top of 4 6nm chiplets. The 5nm chiplets are undoubtedly the compute logic chipets – i.e. the CPU and GPU chiplets – though a precise breakdown of what’s what is not available. A reasonable guess at this point would be 3 CPU chiplets (8 Zen 4 cores each) paired with possibly 6 GPU chiplets; though there's still some cache chiplets unaccounted for. Meanwhile, taking AMD’s “on top of” statement literally, the 6nm chiplets would then be the base dies all of this sits on top of. Based on AMD’s renders, it looks like there’s 8 HBM3 memory stacks in play, which implies around 5TB/second of memory bandwidth, if not more. I cant get this to add up when I look at the photo of the chip. Maybe this is the lower layer we have photographed? The photo is a central cluster of 4 huge chiplets, then and 2+2 big+small chiplets next to each. At first I was trying to imagine this as the top layer, the 9 5nm chiplets, and just couldn't square it. Maybe the 2+2 are all cache/hbm, and this is the 4 6nm chiplets we're seeing? I wonder if that means the 9 compute chiplets are burried in the stack, but the words "on top" keep making me think otherwise. Or perhaps this photo isn't a complete chip, is missing the top dies? I'm still more excited to know about how this all connects than anything else. There's such a huge amount of switching required to connect this all. This feels like such a radical change for Infinity Fabric, such a huge step function.