3 ms·

I took a closer look. As you suggested, LEA reg1,reg2 will simply run the micro-instruction "IND→N RNI" without doing any effective address calculation first. W

by kens 4y ago

I took a closer look. As you suggested, LEA reg1,reg2 will simply run the micro-instruction "IND→N RNI" without doing any effective address calculation first. Whatever address is in the IND (Indirect) register will be written to the register specified in the reg field. As for JMP FAR rm with a register, what I seen in the microdcode doesn't quite match the linked discussion. The microcode is IND → tmpC INC2 tmpC JMP FAR rm Σ → IND SUSP tmpB → PC R DS,P0 OPR → CS FLUSH RNI So it will add 2 to the hidden IND register, read the segment value from that address, and put that in the CS register. Meanwhile, the PC gets the value from the hidden ALU temporary B register. As for the mystery FF FF instruction, I think it jumps into "PUSH rm" and ends up pushing DI. SP → tmpA DEC2 tmpA PUSH rm Σ → IND Σ → SP M → OPR W SS,P0 RNI

userbinator 4y ago
As for the mystery FF FF instruction, I think it jumps into "PUSH rm" and ends up pushing DI. In other words, it seems that FF/6 (the normal "PUSH rm") and FF/7 (officially undefined) are aliases? The other notable anomaly is that 8F/1-7 are also officially undefined, while "POP rm" is at 8F/0. Ignoring the 0F-prefixed ones (POP CS, everyone knows that one by now), there are some interesting gaps in the group table: https://www.sandpile.org/x86/opc_grp.htm https://www.sandpile.org/x86/opc_grp.htm Perhaps all those undefined opcodes could be worth writing another detailed article about, now that you've become familiar with how the instruction decoding works.