In the case of fine grained parallelism, where named registers allow parallelism that a rigid stack evaluation doesn't -- one can decode the stack instructions

In the case of fine grained parallelism, where named registers allow parallelism that a rigid stack evaluation doesn't -- one can decode the stack instructions using a counter, the stack pointer, assign register numbers off the counter, and generate register-based micro-instructions that can be executed out of order or in parallel in the usual fashion. In this scheme the stack is stored in the register file, and the execution unit (or register-fetch phase if you prefer) has random access to registers.