3 ms·
> It just comes down to the cost of saving/restoring register state (more or less), and that's a nice known fixed cost on any given processor. There's also the
by nordsieck 4y ago
> It just comes down to the cost of saving/restoring register state (more or less), and that's a nice known fixed cost on any given processor.
There's also the cost of cache eviction. Not something you have to manually manage, but it's a cost you pay nonetheless. Maybe.
- PaulDavisThe1st 4y agoIndeed, I ought to have mentioned the cost of cache misses post-context switch too. It too is working set size dependent, but the relationship looks different from the cost of TLB misses. However, my understanding is that an inter-task thread switch would also not cause cache invalidation (there's no need; the address space remains the same).