4 ms·
About the area, keep in mind that not every part of a chip is composed of dense logic: Typically, sram (cache memories for example) doesn't scale as much as co
by SuchAnonMuchWow 4y ago
About the area, keep in mind that not every part of a chip is composed of dense logic:
Typically, sram (cache memories for example) doesn't scale as much as core logic, and interconnect (connections between the cores, DDR, etc...) almost don't scale at all.
This is highly dependent on the design of the SoC, but the core logic is rarely the largest of the three, so you will not see a 35% reduction of the total area of the chip: only of the areas the most densely packed with logic. What you could have for example is a 35% more powerful neural network accelerator in the same area as the previous generation. But you will not have 35% bigger cache.
- nsteel 4y agoHave you seen the 3nm SRAM scaling? It's really depressing. It won't bother CPUs too much but other devices are going to struggle to scale.
- hajile 4y agoN3 scaling? There's literally zero scaling. N3 is a stop-gap as TSMC is behind on their N2 GAA process. It's not so different from Intel's 14nm++++++ where it was dramatically better than before, but still not enough.
- warrenm 4y ago> About the area, keep in mind that not every part of a chip is composed of dense logic No, but improving density still makes it smaller (for an otherwise-"identical" offering) :)