5 ms·

Every generation of shrink has pushed a company or two out of the fab business. I would guess that around 10-12 angstroms TSMC, Samsung, or Intel will cease bei

Every generation of shrink has pushed a company or two out of the fab business. I would guess that around 10-12 angstroms TSMC, Samsung, or Intel will cease being competitive at the leading edge and fold. Most likely that will happen one more time before the shrinking is no longer physically possible while maintaining chip function.

cubefox 4y ago
Physical impossibility probably won't be a factor, since, long before that, process improvements will become so expensive that they don't make economic sense. It doesn't help having a marginally more efficient chip for a much higher price.
chrisjc 4y ago
"When" that happens, I'm extremely curious how and if the remaining incumbents will be able to leverage their dominant positions/technology/ip/etc to establish a footing in whatever new technology supplants the existing. I'm not really talking about whether they'll be too ignorant to recognize the impending existential risk and take action, but these companies are much more than just ASML customers that know how to use lithograph machines. They have layered stacks of mind boggling processes, expertise and experience. Will this new technology be so revolutionary and disruptive that all their advantages are rendered obsolete insofar as competing in this new arena. I guess if anyone could answer any of these questions they wouldn't be sitting around here talking about it on HN :)
sylware 4y ago
Allright, then an optimistic estimate of 3 times to "wrap up" the transistor skrinking with current tech. Then some dies (or chiplet) will probably grow and consume more electricity: I am thinking GPUs... if they can be fed enough data fast enough though. Look at apple Mx dies. That said, I have still no idea of the geometry of a transistor on a die to get an idea of how far we are (and I am not even talking about ion dopping not working properly anymore).
- BirAdam 4y ago
  As for true geometry, current 5nm at TSMC is actually a gate pitch (spacing between the gates) of 51nm and interconnect (smallest possible distance between the centers of adjacent wires on interconnect metal layers) of 28nm. Intel 4 is 50nm gate pitch and 30nm interconnect. So, they're between 1nm of each other. As an example, IBM did create 5nm transistors on silicon nanosheets with GAAFETs in 2017. The spacing between the transistors then had to be 41nm to mitigate quantum tunneling. In the case of TSMC and Intel, their transistors are not at the actual sizes specified, but it is currently not clear that much would be gained if they were if the pitch still had to be so long. NOTE: I am an amateur, so please don't take any of that as actionable fact.
  - ls612 4y ago
    But the "5nm" label still has meaning insofar as a "3nm" process allows proportionally more density (5/3 increase) right? I guess the trillion dollar question is how many more node shrinks are left before quantum tunneling problems overwhelm solutions to them.
    - BirAdam 4y ago
      That is correct. We would expect some kind of fractional shrink equivalent to the numbering system used. Intel expects to shrink from 4 to 3 to 20A and finally 18A. Apparently, decent progress has been made on 20A, so at least 3 shrinks should be expected. TSMC has a roadmap to 2nm, and they expect to slow down after that. Samsung has plans for 1.4nm. My guess is that one major player to fall out around the 20, 18, 14 angstrom area. My present thought is that this will be Samsung. I think expect one or two shrinks before Intel or TSMC falls away. One more after that, and then some other technology may need to step up to the plate. I had long thought that something like gallium arsenide would replace silicon allowing for higher frequencies, but cost might be prohibitive. The world after the shrinks may just be a logic and efficiency war.
      - sylware 4y ago
        I wish we would get a picture with all those metrics. That said, all of those metrics seem huge to what EUV HighNA can do: I remember near "perfect" 7nm "lines" in photoresist. I wonder what is the resolution of the motors to align all that (I guess piezo electric). And interferometers for alignment, x-rays??

cubefox 4y ago

Physical impossibility probably won't be a factor, since, long before that, process improvements will become so expensive that they don't make economic sense. It doesn't help having a marginally more efficient chip for a much higher price.

chrisjc 4y ago

"When" that happens, I'm extremely curious how and if the remaining incumbents will be able to leverage their dominant positions/technology/ip/etc to establish a footing in whatever new technology supplants the existing. I'm not really talking about whether they'll be too ignorant to recognize the impending existential risk and take action, but these companies are much more than just ASML customers that know how to use lithograph machines. They have layered stacks of mind boggling processes, expertise and experience. Will this new technology be so revolutionary and disruptive that all their advantages are rendered obsolete insofar as competing in this new arena. I guess if anyone could answer any of these questions they wouldn't be sitting around here talking about it on HN :)

sylware 4y ago

Allright, then an optimistic estimate of 3 times to "wrap up" the transistor skrinking with current tech. Then some dies (or chiplet) will probably grow and consume more electricity: I am thinking GPUs... if they can be fed enough data fast enough though. Look at apple Mx dies. That said, I have still no idea of the geometry of a transistor on a die to get an idea of how far we are (and I am not even talking about ion dopping not working properly anymore).

BirAdam 4y ago
As for true geometry, current 5nm at TSMC is actually a gate pitch (spacing between the gates) of 51nm and interconnect (smallest possible distance between the centers of adjacent wires on interconnect metal layers) of 28nm. Intel 4 is 50nm gate pitch and 30nm interconnect. So, they're between 1nm of each other. As an example, IBM did create 5nm transistors on silicon nanosheets with GAAFETs in 2017. The spacing between the transistors then had to be 41nm to mitigate quantum tunneling. In the case of TSMC and Intel, their transistors are not at the actual sizes specified, but it is currently not clear that much would be gained if they were if the pitch still had to be so long. NOTE: I am an amateur, so please don't take any of that as actionable fact.
- ls612 4y ago
  But the "5nm" label still has meaning insofar as a "3nm" process allows proportionally more density (5/3 increase) right? I guess the trillion dollar question is how many more node shrinks are left before quantum tunneling problems overwhelm solutions to them.
  - BirAdam 4y ago
    That is correct. We would expect some kind of fractional shrink equivalent to the numbering system used. Intel expects to shrink from 4 to 3 to 20A and finally 18A. Apparently, decent progress has been made on 20A, so at least 3 shrinks should be expected. TSMC has a roadmap to 2nm, and they expect to slow down after that. Samsung has plans for 1.4nm. My guess is that one major player to fall out around the 20, 18, 14 angstrom area. My present thought is that this will be Samsung. I think expect one or two shrinks before Intel or TSMC falls away. One more after that, and then some other technology may need to step up to the plate. I had long thought that something like gallium arsenide would replace silicon allowing for higher frequencies, but cost might be prohibitive. The world after the shrinks may just be a logic and efficiency war.
    - sylware 4y ago
      I wish we would get a picture with all those metrics. That said, all of those metrics seem huge to what EUV HighNA can do: I remember near "perfect" 7nm "lines" in photoresist. I wonder what is the resolution of the motors to align all that (I guess piezo electric). And interferometers for alignment, x-rays??