I'm a digital physical design engineer. Even though the 7nm number is kind of meaningless these days it is still useful to compare the scale. The flip chip bu

I'm a digital physical design engineer. Even though the 7nm number is kind of meaningless these days it is still useful to compare the scale. The flip chip bumps on the top metal layer interface to the outside world. Then they get distributed out to the pins of the package which connect to the socket on the motherboard. Socket AM4 has 1331 pins. Socket SP5 for the Epyc has 6096 pins. I've worked on some chips with over 10,000 bump/pins. A modern chip has over 16 metal layers, with multiple via layers in between and probably another 40-60 base layers with the transistors. The technology to align the masks for each layer is on the nanometer level. In contrast the bumps for the chip to package are in the hundreds of micron level. If we just go with 130 microns / 7 nanometers = 18,571 less precise for the alignment of the package vs alignment of the next mask layer while making the chip. So it is certainly impressive to line up chips on the package but nowhere close to the precision for the mask layers