Yes, One branch unit per SIMD. Though actually 16 IPs, for the 16 hardware threads that can be multiplexed in to hide memory latency, similar to SMT on CPUs. C

Yes, One branch unit per SIMD. Though actually 16 IPs, for the 16 hardware threads that can be multiplexed in to hide memory latency, similar to SMT on CPUs. CUs don't really exist anymore as of RDNA 1, replaced by the WGP. In some marketing materials, AMD brand the workgroup processors as "dual CUs". But that's mostly so people can do per-CU preformance comparisons across generations. Because the number of lanes per SIMD doubled from 16 to 32. Both the WGP and CU have 4 "SIMDs" But the SIMDs in GCN used to be less independent, it was only the vector ALUs and vector registers that were in the SIMDs. All instruction decoding, the branch prediction and scalar ALUs per CU. But to really confuse issues, each SIMD still had its own set of instruction pointers (10 of them for upto 10 hardware threads) and could branch independently. The CU would do a round robin, executing an instruction one of the SIMDs each cycle, so that each SIMD executed an instruction once every 4 cycles. I guess the SIMD name made more sense back in the GCN days were it really was just the vector units, vector registers and a set of IPs. But now RDNA moved the full instruction decoding and branch unit and scalar registers into the SIMD.