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Does anyone know how they place the chiplets on to the blue substrate? It must be incredibly precise, presumably?

by rwmj 4y ago

bfrog 4y ago
Maybe, I wonder if this can work like ic placement on pcbs where surface tension can help align things (solder will pull parts into place) I too would love to know as well!
XzAeRosho 4y ago
Most of those techniques and machinery is behind company secrecy, but yes, you need highly precise and specialized machinery to build that kind of things. Linus Tech Tips did a tour of the Intel fab factory a few months ago: https://www.youtube.com/watch?v=2ehSCWoaOqQ https://www.youtube.com/watch?v=2ehSCWoaOqQ
tyingq 4y ago
This doc has some info about current pitch size for the "bump map" of where the chiplets connect to the substrate. https://www.opencompute.org/documents/odsa-openhbi-l-v1-0-rc2-1-pdf https://www.opencompute.org/documents/odsa-openhbi-l-v1-0-rc... Page 38 says "OpenHBI-L specifies the minimum bump pitch (min) to range from 110um to 130um for manufacturability considerations". Edit: Also related and interesting... "One of the key points AMD spoke about...is how each of the silicon dies are attached to the package. In order to enable a pin-grid array desktop processor, the silicon has to be affixed to the processor in a BGA fashion. AMD stated that due to the 7nm process, the bump pitch ...reduced from 150 microns on 12nm to 130 microns on 7nm. This doesn’t sound like much, however AMD stated that there are only two vendors in the world with technology sufficient to do this." https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/5 https://www.anandtech.com/show/14525/amd-zen-2-microarchitec...
- deleted 4y ago
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- lizknope 4y ago
  I'm a digital physical design engineer. Even though the 7nm number is kind of meaningless these days it is still useful to compare the scale. The flip chip bumps on the top metal layer interface to the outside world. Then they get distributed out to the pins of the package which connect to the socket on the motherboard. Socket AM4 has 1331 pins. Socket SP5 for the Epyc has 6096 pins. I've worked on some chips with over 10,000 bump/pins. A modern chip has over 16 metal layers, with multiple via layers in between and probably another 40-60 base layers with the transistors. The technology to align the masks for each layer is on the nanometer level. In contrast the bumps for the chip to package are in the hundreds of micron level. If we just go with 130 microns / 7 nanometers = 18,571 less precise for the alignment of the package vs alignment of the next mask layer while making the chip. So it is certainly impressive to line up chips on the package but nowhere close to the precision for the mask layers
pclmulqdq 4y ago
The technology to do this is pretty old, and it's basically just a very precise pick-and-place machine (disclaimer - this is for 3D stacking, not necessarily AMD's thing). The rub is that it doesn't need to be that precise: surface tension from the soldering process will actually correct a small mis-placement as long as you aren't off by too much, so the tolerances are bigger than you think.

Does anyone know how they place the chiplets on to the blue substrate? It must be incredibly precise, presumably?

by rwmj 4y ago

Does anyone know how they place the chiplets on to the blue substrate? It must be incredibly precise, presumably?

Maybe, I wonder if this can work like ic placement on pcbs where surface tension can help align things (solder will pull parts into place) I too would love to know as well!

XzAeRosho 4y ago

Most of those techniques and machinery is behind company secrecy, but yes, you need highly precise and specialized machinery to build that kind of things. Linus Tech Tips did a tour of the Intel fab factory a few months ago: https://www.youtube.com/watch?v=2ehSCWoaOqQ https://www.youtube.com/watch?v=2ehSCWoaOqQ

tyingq 4y ago

This doc has some info about current pitch size for the "bump map" of where the chiplets connect to the substrate. https://www.opencompute.org/documents/odsa-openhbi-l-v1-0-rc2-1-pdf https://www.opencompute.org/documents/odsa-openhbi-l-v1-0-rc... Page 38 says "OpenHBI-L specifies the minimum bump pitch (min) to range from 110um to 130um for manufacturability considerations". Edit: Also related and interesting... "One of the key points AMD spoke about...is how each of the silicon dies are attached to the package. In order to enable a pin-grid array desktop processor, the silicon has to be affixed to the processor in a BGA fashion. AMD stated that due to the 7nm process, the bump pitch ...reduced from 150 microns on 12nm to 130 microns on 7nm. This doesn’t sound like much, however AMD stated that there are only two vendors in the world with technology sufficient to do this." https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/5 https://www.anandtech.com/show/14525/amd-zen-2-microarchitec...

deleted 4y ago
[deleted]
lizknope 4y ago
I'm a digital physical design engineer. Even though the 7nm number is kind of meaningless these days it is still useful to compare the scale. The flip chip bumps on the top metal layer interface to the outside world. Then they get distributed out to the pins of the package which connect to the socket on the motherboard. Socket AM4 has 1331 pins. Socket SP5 for the Epyc has 6096 pins. I've worked on some chips with over 10,000 bump/pins. A modern chip has over 16 metal layers, with multiple via layers in between and probably another 40-60 base layers with the transistors. The technology to align the masks for each layer is on the nanometer level. In contrast the bumps for the chip to package are in the hundreds of micron level. If we just go with 130 microns / 7 nanometers = 18,571 less precise for the alignment of the package vs alignment of the next mask layer while making the chip. So it is certainly impressive to line up chips on the package but nowhere close to the precision for the mask layers

pclmulqdq 4y ago

The technology to do this is pretty old, and it's basically just a very precise pick-and-place machine (disclaimer - this is for 3D stacking, not necessarily AMD's thing). The rub is that it doesn't need to be that precise: surface tension from the soldering process will actually correct a small mis-placement as long as you aren't off by too much, so the tolerances are bigger than you think.