3 ms·
You're being overly pedantic. They define how they're using it (as a SIMD-capable compute unit) in the article: > Each WGP, or workgroup processor, features fo
by ethbr0 4y ago
You're being overly pedantic. They define how they're using it (as a SIMD-capable compute unit) in the article:
> Each WGP, or workgroup processor, features four SIMDs. [...] Each SIMD has 32-wide execution units for the most common operations, a 128 KB vector register file, and can track up to 16 wavefronts.
- fulafel 4y agoI asked: > What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? Basically I'm interested in how independent these are, can they each go off doing their own thing or not, and what resources are shared with the parent units (wgp and cu)
- ethbr0 4y agoI believe each wavefront has its own instruction pointer. For me, it's easier to think about GPU arch as trying to realize a never-ending stream of data being continually processed, with all other components of a processor redefined to ensure The Stream Never Stops. From that perspective, things like wavefront-attached instructions, data scheduling, execution masking, or bastardized conditional support make more sense. Think of "a cycle" as a set of data first, rather than an instruction/state. https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf https://developer.amd.com/wp-content/resources/RDNA2_Shader_...