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> What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? It's a CPU arch term. Single instruction, multiple data. So
by ethbr0 4y ago
> What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc?
It's a CPU arch term. Single instruction, multiple data. So essentially, 1 instruction pointer that operates on >1 independent pieces of data each cycle. https://en.m.wikipedia.org/wiki/Single_instruction,_multiple_data https://en.m.wikipedia.org/wiki/Single_instruction,_multiple...
Useful to increase performance at lower hardware cost when you're doing the same thing at the same time over a large number of items (i.e. graphics).
> I wonder what else BVH speedups could be used for in eg GPGPU applications. DB queries that have 3 dimensions eg timespan, attribute set, value span?
There was some cool DB acceleration stuff at GTC ~5 years ago(?) doing this with the then-current hardware accelerators.
Unfortunately, it gets into the specialization vs more general hardware tradeoff: it's usually cheaper to keep software the same and throw more hardware at a problem vs specializing software and hardware.
- fulafel 4y agoYes.. But "a SIMD" is not established computer architecture terminology, SIMD is a characteristic of a processor instruction set - but a processor core (or SMT thread thereof) might eg have multiple SIMD execution units. It's like saying "a CISC" or something. So it begs the question, a SIMD what? A SIMD lane, one SIMD unit of many in a multi threaded processor, a SIMD register context of a thread, something else?
- ethbr0 4y agoYou're being overly pedantic. They define how they're using it (as a SIMD-capable compute unit) in the article: > Each WGP, or workgroup processor, features four SIMDs. [...] Each SIMD has 32-wide execution units for the most common operations, a 128 KB vector register file, and can track up to 16 wavefronts.
- fulafel 4y agoI asked: > What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? Basically I'm interested in how independent these are, can they each go off doing their own thing or not, and what resources are shared with the parent units (wgp and cu)
- ethbr0 4y agoI believe each wavefront has its own instruction pointer. For me, it's easier to think about GPU arch as trying to realize a never-ending stream of data being continually processed, with all other components of a processor redefined to ensure The Stream Never Stops. From that perspective, things like wavefront-attached instructions, data scheduling, execution masking, or bastardized conditional support make more sense. Think of "a cycle" as a set of data first, rather than an instruction/state. https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf https://developer.amd.com/wp-content/resources/RDNA2_Shader_...