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> Each WGP, or workgroup processor, features four SIMDs. [...] Each SIMD has 32-wide execution units for the most common operations, a 128 KB vector register fi

> Each WGP, or workgroup processor, features four SIMDs. [...] Each SIMD has 32-wide execution units for the most common operations, a 128 KB vector register file, and can track up to 16 wavefronts. What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? Nice to read a rare explanation mof what the actual HW functionality that can help with ray tracing actually is: > At the CU level [...] the texture unit can now perform ray intersection tests, at a rate of four box tests per cycle or one triangle test per cycle. Box tests take place at upper levels of the BVH, while triangle tests happen at the last level. A BVH, or bounded vertex hierarchy, speeds up raytracing with a divide-and-conquer methodology I wonder what else BVH speedups could be used for in eg GPGPU applications. DB queries that have 3 dimensions eg timespan, attribute set, value span?

ethbr0 4y ago
> What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? It's a CPU arch term. Single instruction, multiple data. So essentially, 1 instruction pointer that operates on >1 independent pieces of data each cycle. https://en.m.wikipedia.org/wiki/Single_instruction,_multiple_data https://en.m.wikipedia.org/wiki/Single_instruction,_multiple... Useful to increase performance at lower hardware cost when you're doing the same thing at the same time over a large number of items (i.e. graphics). > I wonder what else BVH speedups could be used for in eg GPGPU applications. DB queries that have 3 dimensions eg timespan, attribute set, value span? There was some cool DB acceleration stuff at GTC ~5 years ago(?) doing this with the then-current hardware accelerators. Unfortunately, it gets into the specialization vs more general hardware tradeoff: it's usually cheaper to keep software the same and throw more hardware at a problem vs specializing software and hardware.
- fulafel 4y ago
  Yes.. But "a SIMD" is not established computer architecture terminology, SIMD is a characteristic of a processor instruction set - but a processor core (or SMT thread thereof) might eg have multiple SIMD execution units. It's like saying "a CISC" or something. So it begs the question, a SIMD what? A SIMD lane, one SIMD unit of many in a multi threaded processor, a SIMD register context of a thread, something else?
  - ethbr0 4y ago
    You're being overly pedantic. They define how they're using it (as a SIMD-capable compute unit) in the article: > Each WGP, or workgroup processor, features four SIMDs. [...] Each SIMD has 32-wide execution units for the most common operations, a 128 KB vector register file, and can track up to 16 wavefronts.
    - fulafel 4y ago
      I asked: > What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? Basically I'm interested in how independent these are, can they each go off doing their own thing or not, and what resources are shared with the parent units (wgp and cu)
      - ethbr0 4y ago
        I believe each wavefront has its own instruction pointer. For me, it's easier to think about GPU arch as trying to realize a never-ending stream of data being continually processed, with all other components of a processor redefined to ensure The Stream Never Stops. From that perspective, things like wavefront-attached instructions, data scheduling, execution masking, or bastardized conditional support make more sense. Think of "a cycle" as a set of data first, rather than an instruction/state. https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf https://developer.amd.com/wp-content/resources/RDNA2_Shader_...
phire 4y ago
Yeah, an "SIMD" in AMD's terminology is more-or-less an independent "cpu-like" core. Has it's own instruction decoder and multiplexes upto 16 threads of executions (wavefronts) depending on how many registers each thread needs. The SIMD has it's own register files and execution units (ALUs/FPUs). What these SIMDs share with the other 3 SIMDs in the workgroup processor are the caches and memory subsystem (which includes texture units and RT hardware)
- fulafel 4y ago
  Ok. So does each AMD-SIMD unit have its own instruction pointer and branch unit too? I think there used to be one IP per CU earlier...
  - phire 4y ago
    Yes, One branch unit per SIMD. Though actually 16 IPs, for the 16 hardware threads that can be multiplexed in to hide memory latency, similar to SMT on CPUs. CUs don't really exist anymore as of RDNA 1, replaced by the WGP. In some marketing materials, AMD brand the workgroup processors as "dual CUs". But that's mostly so people can do per-CU preformance comparisons across generations. Because the number of lanes per SIMD doubled from 16 to 32. Both the WGP and CU have 4 "SIMDs" But the SIMDs in GCN used to be less independent, it was only the vector ALUs and vector registers that were in the SIMDs. All instruction decoding, the branch prediction and scalar ALUs per CU. But to really confuse issues, each SIMD still had its own set of instruction pointers (10 of them for upto 10 hardware threads) and could branch independently. The CU would do a round robin, executing an instruction one of the SIMDs each cycle, so that each SIMD executed an instruction once every 4 cycles. I guess the SIMD name made more sense back in the GCN days were it really was just the vector units, vector registers and a set of IPs. But now RDNA moved the full instruction decoding and branch unit and scalar registers into the SIMD.
    - fulafel 4y ago
      Good stuff, thanks for the detailed explanation!

ethbr0 4y ago

> What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? It's a CPU arch term. Single instruction, multiple data. So essentially, 1 instruction pointer that operates on >1 independent pieces of data each cycle. https://en.m.wikipedia.org/wiki/Single_instruction,_multiple_data https://en.m.wikipedia.org/wiki/Single_instruction,_multiple... Useful to increase performance at lower hardware cost when you're doing the same thing at the same time over a large number of items (i.e. graphics). > I wonder what else BVH speedups could be used for in eg GPGPU applications. DB queries that have 3 dimensions eg timespan, attribute set, value span? There was some cool DB acceleration stuff at GTC ~5 years ago(?) doing this with the then-current hardware accelerators. Unfortunately, it gets into the specialization vs more general hardware tradeoff: it's usually cheaper to keep software the same and throw more hardware at a problem vs specializing software and hardware.

fulafel 4y ago
Yes.. But "a SIMD" is not established computer architecture terminology, SIMD is a characteristic of a processor instruction set - but a processor core (or SMT thread thereof) might eg have multiple SIMD execution units. It's like saying "a CISC" or something. So it begs the question, a SIMD what? A SIMD lane, one SIMD unit of many in a multi threaded processor, a SIMD register context of a thread, something else?
- ethbr0 4y ago
  You're being overly pedantic. They define how they're using it (as a SIMD-capable compute unit) in the article: > Each WGP, or workgroup processor, features four SIMDs. [...] Each SIMD has 32-wide execution units for the most common operations, a 128 KB vector register file, and can track up to 16 wavefronts.
  - fulafel 4y ago
    I asked: > What do they mean by a "SIMD", is it a independent core with its own instruction pointer(s) etc? Basically I'm interested in how independent these are, can they each go off doing their own thing or not, and what resources are shared with the parent units (wgp and cu)
    - ethbr0 4y ago
      I believe each wavefront has its own instruction pointer. For me, it's easier to think about GPU arch as trying to realize a never-ending stream of data being continually processed, with all other components of a processor redefined to ensure The Stream Never Stops. From that perspective, things like wavefront-attached instructions, data scheduling, execution masking, or bastardized conditional support make more sense. Think of "a cycle" as a set of data first, rather than an instruction/state. https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf https://developer.amd.com/wp-content/resources/RDNA2_Shader_...

phire 4y ago

Yeah, an "SIMD" in AMD's terminology is more-or-less an independent "cpu-like" core. Has it's own instruction decoder and multiplexes upto 16 threads of executions (wavefronts) depending on how many registers each thread needs. The SIMD has it's own register files and execution units (ALUs/FPUs). What these SIMDs share with the other 3 SIMDs in the workgroup processor are the caches and memory subsystem (which includes texture units and RT hardware)

fulafel 4y ago
Ok. So does each AMD-SIMD unit have its own instruction pointer and branch unit too? I think there used to be one IP per CU earlier...
- phire 4y ago
  Yes, One branch unit per SIMD. Though actually 16 IPs, for the 16 hardware threads that can be multiplexed in to hide memory latency, similar to SMT on CPUs. CUs don't really exist anymore as of RDNA 1, replaced by the WGP. In some marketing materials, AMD brand the workgroup processors as "dual CUs". But that's mostly so people can do per-CU preformance comparisons across generations. Because the number of lanes per SIMD doubled from 16 to 32. Both the WGP and CU have 4 "SIMDs" But the SIMDs in GCN used to be less independent, it was only the vector ALUs and vector registers that were in the SIMDs. All instruction decoding, the branch prediction and scalar ALUs per CU. But to really confuse issues, each SIMD still had its own set of instruction pointers (10 of them for upto 10 hardware threads) and could branch independently. The CU would do a round robin, executing an instruction one of the SIMDs each cycle, so that each SIMD executed an instruction once every 4 cycles. I guess the SIMD name made more sense back in the GCN days were it really was just the vector units, vector registers and a set of IPs. But now RDNA moved the full instruction decoding and branch unit and scalar registers into the SIMD.
  - fulafel 4y ago
    Good stuff, thanks for the detailed explanation!