3 ms·
> cache line Wrong side of the L1 cache. Cache-lines is how L1 cache talks to L2/L3 cache. I'm talking about the load/store units in the CPU core, or the Core
by dragontamer 4y ago
> cache line
Wrong side of the L1 cache. Cache-lines is how L1 cache talks to L2/L3 cache.
I'm talking about the load/store units in the CPU core, or the Core <--> L1 cache communications. This side is less commonly discussed online, but I am pretty sure its important in this AVX512 discussion. (To be fair, I probably should have said "Load/Store" unit instead of L1 cache in my previous post, which would have been more clear)
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Modern CPU cores only have a limited number of load/store units. Its superscalar of course, like 4 load/stores per clock tick or something, but still limited. By "batching" your loads/stores into 512-bits instead of 256-bits or 64-bits at a time, your CPU doesn't have to do as much work to talk with L1 cache.
- usrusr 4y agoAh, so it's not so much about adjacency (which would even benefit an implementation that insisted on loading bytes individually) but about the number of operations required to bucket-brigade those zeroes and ones into registerland when the cache issue is solved (which I'd have very much expected to be the case in the baseline of the comparison, just like other replies). I was close to dismissing your reply as merely a nomenclature nitpick, but I think I have learned something interesting, thanks!
- dragontamer 4y agoI definitely didn't use the correct language in my post above. But I think we've got the misunderstanding cleared up now. I'll try to use the word "Load/store Unit" when talking about that part of the CPU from now on.