> x86 has so few general purpose registers, It's got plenty in 64-bit mode (15 + RSP) + you can spill to SSE registers instead of the stack. It also needs few

> x86 has so few general purpose registers, It's got plenty in 64-bit mode (15 + RSP) + you can spill to SSE registers instead of the stack. It also needs fewer registers than (most) RISCs because it has a more flexible way of specifying memory addresses (base, index, scale, offset + PC-relative) and it also has proper immediates. > the highly variable length of x86/x86-64 instructions puts a limit on the number of instructions that can be decoded per cycle. Not that much of a limit, actually. Yes, a parallel decoder that takes on arbitrary byte sequence and decodes them is hard to scale up. The instruction lengths can be cached, though. In fact, they used to be cached as extra bits in L1 back when the size of a wide decoder was a significant size of the CPU transistor budget. It should be possible to use that idea again to go wider. The newer x86 CPU's also have a µop cache so no decoding is even needed for tight loops.