5 ms·

Great job AMD, now do RISC V so Apple's M1 can get some competition.

AlexandrB 4y ago
If they did, what OS would run on it? The only options I know of is Linux or one of the BSDs so you're either looking at the server market (where M1 is not a competitor anyway) or the Linux desktop market, which is small - nothing close to 30% of desktop/laptop PCs.
- cmrdporcupine 4y ago
  I can see server market being a thing, as ARM is just now starting to make inroads there so there might be room for a new emergent RISC market, assuming it could be price/watt competitive. But I agree, it would be a tiny market. Another option is if AMD decided to get into the mobile / embedded SoC market for real, and didn't want to pay an ARM license to do it.
quelsolaar 4y ago
Actually RISC-V is worse than x64 when it comes to performance per watt. It is designed to be very simple, not to be efficient. It does not natively have common instructions like add multiply. To make an efficient modern processor, you want to larger more specialized instructions that do more per clock cycle and have dedicated hardware for common tasks.
- cmrdporcupine 4y ago
  "It does not natively have common instructions like add multiply"; this is is misinformation. Almost anybody implementing RISC-V -- esp if they are targeting an MPU instead of MCU -- is implementing instruction variants which include signed and unsigned multiply and divide, and my understanding is the P and probably V extensions include various add-multiply instructions. https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.pdf https://github.com/riscv/riscv-p-spec/blob/master/P-ext-prop... See section 3.2. The instruction set is specified in a 'modular' fashion and has standards for various extensions, including compact instructions, vector extensions, etc. Compilers like GCC and LLVM support targeting these extensions. I'm not saying AMD should make a RISC-V CPU, but if they were to hypothetically do that, they'd clearly be including a pile of the ratified extensions.
- monocasa 4y ago
  RISC-V is designed to be efficient; when compared on the same litho processes and gate counts it's very competitive wrt perf/watt.
- zik 4y ago
  You might want to check your sources on that. Everything you said is wrong.
- mort96 4y ago
  > To make an efficient modern processor, you want to larger more specialized instructions that do more per clock cycle No, not really. The large specialized instructions in x86 run across many, many clock cycles. And IIRC, compilers will often generate a sequence of simple instructions rather than one complex instruction, because the CPUs are so much better at executing sequences of simple instructions. (And yeah, as others have pointed out, of course high end RISC-V chips have multiply and divide instructions with dedicated multiply and divide hardware.)

If they did, what OS would run on it? The only options I know of is Linux or one of the BSDs so you're either looking at the server market (where M1 is not a competitor anyway) or the Linux desktop market, which is small - nothing close to 30% of desktop/laptop PCs.

cmrdporcupine 4y ago
I can see server market being a thing, as ARM is just now starting to make inroads there so there might be room for a new emergent RISC market, assuming it could be price/watt competitive. But I agree, it would be a tiny market. Another option is if AMD decided to get into the mobile / embedded SoC market for real, and didn't want to pay an ARM license to do it.

quelsolaar 4y ago

Actually RISC-V is worse than x64 when it comes to performance per watt. It is designed to be very simple, not to be efficient. It does not natively have common instructions like add multiply. To make an efficient modern processor, you want to larger more specialized instructions that do more per clock cycle and have dedicated hardware for common tasks.

cmrdporcupine 4y ago
"It does not natively have common instructions like add multiply"; this is is misinformation. Almost anybody implementing RISC-V -- esp if they are targeting an MPU instead of MCU -- is implementing instruction variants which include signed and unsigned multiply and divide, and my understanding is the P and probably V extensions include various add-multiply instructions. https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.pdf https://github.com/riscv/riscv-p-spec/blob/master/P-ext-prop... See section 3.2. The instruction set is specified in a 'modular' fashion and has standards for various extensions, including compact instructions, vector extensions, etc. Compilers like GCC and LLVM support targeting these extensions. I'm not saying AMD should make a RISC-V CPU, but if they were to hypothetically do that, they'd clearly be including a pile of the ratified extensions.
monocasa 4y ago
RISC-V is designed to be efficient; when compared on the same litho processes and gate counts it's very competitive wrt perf/watt.
zik 4y ago
You might want to check your sources on that. Everything you said is wrong.
mort96 4y ago
> To make an efficient modern processor, you want to larger more specialized instructions that do more per clock cycle No, not really. The large specialized instructions in x86 run across many, many clock cycles. And IIRC, compilers will often generate a sequence of simple instructions rather than one complex instruction, because the CPUs are so much better at executing sequences of simple instructions. (And yeah, as others have pointed out, of course high end RISC-V chips have multiply and divide instructions with dedicated multiply and divide hardware.)