> the failure to clock higher was IMO largely due to a ridiculously bloated and over-complicated ISA. Perhaps mostly due to having too many architected regist

> the failure to clock higher was IMO largely due to a ridiculously bloated and over-complicated ISA. Perhaps mostly due to having too many architected registers AND making most of them rotating/part of register windows... that means more work to do per instruction. Wide superscalar => you need lots and lots of forwarding paths between the ALUs. Combined with no out of order execution to allow for spreading that work out a bit (longer latencies per instruction but largely hidden by other work) and you get hard limits on the clock speed. The ISA wasn't actually that bloated.