Those who want "excitement" in instruction sets should study GPUs, POWER10, ARMv8, AVX512, and ARM's SVE these days. GPU instructions, such as bpermute, permut

Those who want "excitement" in instruction sets should study GPUs, POWER10, ARMv8, AVX512, and ARM's SVE these days. GPU instructions, such as bpermute, permute, warp-vote, and other such concepts are the biggest "conceptual" changes to compute I've ever seen. DirectX12, Vulkan, CUDA, HIP, it doesn't really matter what you study per se, the GPU community knows brute force performance and is advancing it. From this perspective, your study guides are the NVidia PTX guide (CUDA's assembly language), and AMD's RDNA2 ISA. Also keep in mind the NVidia PTX wgmma instruction, which is key to 16-bit 4x4 matrix multiplications (aka: Deep Learning / Tensors). NVidia's underlying assembly is undocumented (instead, hidden away by the PTX layer / compiler). But people have been figuring out how it works under the hood. I don't think NVidia is trying to keep it a secret, as much as they just prefer users to work at the PTX layer, which would be more portable in the long term. Studying this SASS assembly is harder but still possible: https://arxiv.org/abs/2208.11174 https://arxiv.org/abs/2208.11174 --------- x86-wise, the pext and pdep instructions are single-cycle gather/scatter bitwise operations over 64-bits. I consider these to be the greatest advancements to compute theory on the x86 side and highly suggest people to play with these instructions. They're incredible. POWER and ARMv8 have extremely clean implementations of load-acquire / store-release, and I expect this to be fundamental to large-scale scaling of CPUs, cache-coherence, and even I/O in the long run. ------- AVX512 and SVE are other ideas into SIMD compute. AVX512 has compress instructions that I think work extremely well for common SIMD code (ex: the stream compression problem). SVE tries to be agnostic with SIMD-width. A noble effort, but its the odd one out (AVX512, NVidia CUDA, and AMD HIP all rely upon static SIMD-widths). I'm still interested in what it can do with its "SIMD-width agnostic" framework, but I also recognize that it stands alone in today's ISAs. -------- The closest thing to Intel Itanium is probably Xilinx FPGAs, which I'm told are VLIW-based instructions still. The old Itanium went all in on VLIW, but its just not a popular ISA-style today, and is largely considered "defeated". But VLIW apparently lives on in DSPs and Xilinx FPGAs. While no one seems to be investing in this concept, its still being studied (by at least DSP programmers) and could be a darkhorse comeback in 10 years or so.