If design objectives generally pin delay to the short side of what is possible, perhaps making it shorter is hard? I don't actually know if this is the case an

If design objectives generally pin delay to the short side of what is possible, perhaps making it shorter is hard? I don't actually know if this is the case and I could see how it might not be. If you only need to do it in one gate maybe you can just burn a bit more power in that particular gate. It's not a strategy that would scale to the whole chip, so the designer can't follow it, but a saboteur isn't optimizing the whole chip so it works for that purpose.