Waveform tests, delay tests, and empty "fill" die checks, to boil it down. Waveform requires one to take the time to enable checking all possible input values,

Waveform tests, delay tests, and empty "fill" die checks, to boil it down. Waveform requires one to take the time to enable checking all possible input values, not just ones that "actually do something" in the design. It also looks really tedious, and probably has automation. Delay can be used because each logic gate has some arbitrary but known delay, and inserting a rogue gate into a design increases such latency by enough that it's easy - for now - to spot. I'll revisit this if i have time, below. Finally, fill space may be required if the logic table dictates that the actual gates must be in specific areas to not introduce delay or increase power consumption. This part was a little scant, but it seemed interesting. As far as the delay goes, changing one logic gate to another kind seems like it wouldn't introduce extra delay steps, but i think the implication is - as i said - the delays of various ICs in the "known good" are known. If this is actually feasible, changing one gate to have a longer delay and another to have a shorter delay; the shorter delay not necessarily being malicious, and doesn't break the design - wouldn't these cancel out and make the delay testing less reliable?