I don't think building a threaded cpu that switches threads to hide memory latency would be philosophically incompatible with VLIW. I think the later generatio

I don't think building a threaded cpu that switches threads to hide memory latency would be philosophically incompatible with VLIW. I think the later generation itaniums were threaded too. VLIW might make it hard to share functional units, but don't-- the relatively simplicity of the core should let you have more copies of the whole shabang. The SMT would just be for hiding memory accesses not for higher functional unit utilization. On x86 SMT gets a bad rap because its never been tremendously effective. It's much more effective in IBM's implementation on Power. It wouldn't be hard to imagine some Itanium SMT monster.