4 ms·
The PA-RISC 1.1 ISA encoded specific implementation details that didn't age well, like the branch delay slot and instruction address queues. And required in-ord
by rsaxvc 4y ago
The PA-RISC 1.1 ISA encoded specific implementation details that didn't age well, like the branch delay slot and instruction address queues. And required in-order memory accesses, because there wasn't support for cache coherent IO.
- ghaff 4y agoAnd, at a higher level, Unix vendor-specific processor designs were on the way out. Designing and manufacturing a processor just for your relatively low volumes in the scheme of things Unix systems was just way too expensive. One of the other problems with Itanium was that it was supposed to be an "industry standard" 64-bit processor. But Intel and HP were never quite able to square that with a situation where HP at least saw themselves as more equal than others given their role in the design.