5 ms·
If you know how long data will take to go to/from memory then you can schedule pretty well. If you don't know whether some value will hit in the L1 or the L3 c
by JonChesterfield 4y ago
If you know how long data will take to go to/from memory then you can schedule pretty well.
If you don't know whether some value will hit in the L1 or the L3 cache there's wild variance on how long it'll take so you have to do something else in the meantime. On x64, that's the pipeline and speculation. On a GPU, you swap to another fibre/warp until the memory op finished.
Fundamentally the hardware knows how long the memory access took, the software can only guess how long it will take. That kills effective ahead of time scheduling on most architectures.
- throwawaymaths 4y agoIirc caches mostly exist to help keep pipelines full. You could maybe imagine an architecture with deterministic memory access times from specified regions.
- cwzwarich 4y agoSuch architectures exist (e.g. for signal processing). They just aren't good for running general-purpose software.
- Kon-Peki 4y agoItanium sold, barely, and still has people using it. But, as you can imagine, not with general-purpose software. By the 2nd or 3rd generation, Intel had made some changes that really improved performance a lot. Was the final generation of Itanium the 4th generation?
- nordsieck 4y ago> You could maybe imagine an architecture with deterministic memory access times from specified regions. Sure. But it's very easy to level down. And almost impossible to level up.
- anonymoushn 4y ago> Iirc caches mostly exist to help keep pipelines full You can find out by disabling the stride prefetcher and observing the 90+% performance regression in all your software!
- nullc 4y agoI don't think building a threaded cpu that switches threads to hide memory latency would be philosophically incompatible with VLIW. I think the later generation itaniums were threaded too. VLIW might make it hard to share functional units, but don't-- the relatively simplicity of the core should let you have more copies of the whole shabang. The SMT would just be for hiding memory accesses not for higher functional unit utilization. On x86 SMT gets a bad rap because its never been tremendously effective. It's much more effective in IBM's implementation on Power. It wouldn't be hard to imagine some Itanium SMT monster.
- yosefk 4y agoHow many threads would it take to hide 100ns of DRAM access latency and what serial performance would we get?
- nullc 4y agoIt doesn't have to be hidden completely, there are still caches. With 2 unstalled threads you effectively halve it (in terms of throughput), 4 unstalled threads you effectively quarter it, etc.
- Kon-Peki 4y ago> It wouldn't be hard to imagine some Itanium SMT monster. Itanium did have SMT
- deleted 4y ago[deleted]