Does the core area math check out on that? Is the x86 instruction decoding area a small enough part of today's cores that having a chip that includes both a RIS

Does the core area math check out on that? Is the x86 instruction decoding area a small enough part of today's cores that having a chip that includes both a RISC-V decoder and a x86 one not a big penalty? It's also not clear that would be a gain for AMD. x86 has a lot of lock-in and AMD is one of two viable suppliers of it. Helping along a RISC-V transition would create opportunities for attackers that don't need to license x86. AMD doesn't seem to have a reason for that right now. But maybe that's an Innovator's Dilemma kind of situation and they should be cannibalizing the present to setup their future.