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Itanium was a second Intel VLIW design. The first one was the i860, which was a mixed bag of either being eye popping fast, if instruction bundles were handcraf

Itanium was a second Intel VLIW design. The first one was the i860, which was a mixed bag of either being eye popping fast, if instruction bundles were handcrafted by a human, or being as slow as a dog if it was a compiler that emitted the code. Perhaps, there was a belief back then that compilers could be easily optimised or uplifted to generate fast and efficient code, and that did not turn out to be the case. Project management and mismanagement certainly did not help either. I wonder how a VLIW architecture would pan out today given advances in compilers in last three decades, and whether a ML assisted VLIW backend could deliver on the old dream.

pclmulqdq 4y ago
GPUs today have a more VLIW-like architecture than CPUs and almost every neural network accelerator is a VLIW chip of some kind. It's worked out really well. The big problem is SMT, since it's hard to share a VLIW core between processes, while a superscalar core shares really well.
- inkyoto 4y ago
  Indeed. RISC-V instruction fusion is a little bit VLIW like. I wonder how it handles the fused instruction transition across CPU cores tho (I have not looked into it).
  - pclmulqdq 4y ago
    Most superscalar cores do macro-op fusion, including ARM and x86. They don't transition the fused op - it usually executes in one cycle (which is the point of the fusion) so you transition either before or after it.
- cwzwarich 4y ago
  > GPUs today have a more VLIW-like architecture than CPUs Older GPUs seemed more VLIW-like because they were descended from fixed-function rendering pipelines and essentially just exposed the control signals via instruction encodings. Over time, shader cores have become less VLIW-like, e.g. look at any reverse engineering of recent Nvidia architectures. This makes sense for the same reason you give for SMT: if you're trying to execute from multiple instruction streams on the same execution units, it makes more sense to use small individual instructions rather than large puzzle pieces.
- raphlinus 4y ago
  I wouldn't describe a GPU architecture as VLIW-like, though there is some overlap. To me, the essence of VLIW is extracting instruction level parallelism by specifying lots of different operations in the same instruction word. To this end, the instruction word has to be quite big (128 bits on Itanium) to specify all those operations. A modern CPU has the same goal of extracting ILP but accomplishes it in a very different way. The instruction stream is short instructions, each of which specifies a simple operation, and these are reassembled using sophisticated dynamic logic into micro-ops, which then get executed in a fairly similar fashion as a VLIW machine - there are a large number of ports (8 is fairly typical these days), each of which performs a separate operation such as arithmetic, load/store, branch, etc. A GPU has a similar goal of extracting lots of parallelism but does it in a very different way to both VLIW and modern superscalar CPUs. Each instruction operates over a large SIMD vector - 32 is typical, but this varies from 8 (Intel SIMD-8) to 128 (Imagination & optionally Adreno). The instruction specifies many copies of the same operation, so doesn't have to be that big. On RDNA3 for example[1], the basic instruction size is 32 bits, but 64 bits is also common (see section 6.1 for a summary of scalar and 7.1 for a summary of vector encodings). These instruction sizes are a bit bigger than typical for CPU, for two main reasons. First, there are a lot of registers (256 vector registers), so that needs a lot of bits to encode. Second, it's common to add extra operations such as negation or absolute value in the same operation. But these operations are generally fairly inexpensive modifications on existing data, not completely separate as in VLIW. In general, execution on a GPU is in-order, so all the reorder buffers and other techniques of superscalar CPUs are not used. Instead of trying to extract as much parallelism as possible from a single thread, a GPU will use that transistor budget to splat more execution units (and thus more threads) on the chip. [1]: https://developer.amd.com/wp-content/resources/RDNA3_Shader_ISA_December2022.pdf https://developer.amd.com/wp-content/resources/RDNA3_Shader_...
- egorpv 4y ago
  ATI/AMD used VLIW-based TeraScale sometime in 2007-2011 [1], although some stories claim it started even earlier [2], but in any case they later dropped it in favor of RISC-based GCN. And I'm not sure if Nvidia ever had anything VLIW-based at all. [1] https://en.wikipedia.org/wiki/TeraScale_(microarchitecture) https://en.wikipedia.org/wiki/TeraScale_(microarchitecture) [2] https://www.anandtech.com/show/4455/amds-graphics-core-next-preview-amd-architects-for-compute/2 https://www.anandtech.com/show/4455/amds-graphics-core-next-...

pclmulqdq 4y ago

GPUs today have a more VLIW-like architecture than CPUs and almost every neural network accelerator is a VLIW chip of some kind. It's worked out really well. The big problem is SMT, since it's hard to share a VLIW core between processes, while a superscalar core shares really well.

inkyoto 4y ago
Indeed. RISC-V instruction fusion is a little bit VLIW like. I wonder how it handles the fused instruction transition across CPU cores tho (I have not looked into it).
- pclmulqdq 4y ago
  Most superscalar cores do macro-op fusion, including ARM and x86. They don't transition the fused op - it usually executes in one cycle (which is the point of the fusion) so you transition either before or after it.
cwzwarich 4y ago
> GPUs today have a more VLIW-like architecture than CPUs Older GPUs seemed more VLIW-like because they were descended from fixed-function rendering pipelines and essentially just exposed the control signals via instruction encodings. Over time, shader cores have become less VLIW-like, e.g. look at any reverse engineering of recent Nvidia architectures. This makes sense for the same reason you give for SMT: if you're trying to execute from multiple instruction streams on the same execution units, it makes more sense to use small individual instructions rather than large puzzle pieces.
raphlinus 4y ago
I wouldn't describe a GPU architecture as VLIW-like, though there is some overlap. To me, the essence of VLIW is extracting instruction level parallelism by specifying lots of different operations in the same instruction word. To this end, the instruction word has to be quite big (128 bits on Itanium) to specify all those operations. A modern CPU has the same goal of extracting ILP but accomplishes it in a very different way. The instruction stream is short instructions, each of which specifies a simple operation, and these are reassembled using sophisticated dynamic logic into micro-ops, which then get executed in a fairly similar fashion as a VLIW machine - there are a large number of ports (8 is fairly typical these days), each of which performs a separate operation such as arithmetic, load/store, branch, etc. A GPU has a similar goal of extracting lots of parallelism but does it in a very different way to both VLIW and modern superscalar CPUs. Each instruction operates over a large SIMD vector - 32 is typical, but this varies from 8 (Intel SIMD-8) to 128 (Imagination & optionally Adreno). The instruction specifies many copies of the same operation, so doesn't have to be that big. On RDNA3 for example[1], the basic instruction size is 32 bits, but 64 bits is also common (see section 6.1 for a summary of scalar and 7.1 for a summary of vector encodings). These instruction sizes are a bit bigger than typical for CPU, for two main reasons. First, there are a lot of registers (256 vector registers), so that needs a lot of bits to encode. Second, it's common to add extra operations such as negation or absolute value in the same operation. But these operations are generally fairly inexpensive modifications on existing data, not completely separate as in VLIW. In general, execution on a GPU is in-order, so all the reorder buffers and other techniques of superscalar CPUs are not used. Instead of trying to extract as much parallelism as possible from a single thread, a GPU will use that transistor budget to splat more execution units (and thus more threads) on the chip. [1]: https://developer.amd.com/wp-content/resources/RDNA3_Shader_ISA_December2022.pdf https://developer.amd.com/wp-content/resources/RDNA3_Shader_...
egorpv 4y ago
ATI/AMD used VLIW-based TeraScale sometime in 2007-2011 [1], although some stories claim it started even earlier [2], but in any case they later dropped it in favor of RISC-based GCN. And I'm not sure if Nvidia ever had anything VLIW-based at all. [1] https://en.wikipedia.org/wiki/TeraScale_(microarchitecture) https://en.wikipedia.org/wiki/TeraScale_(microarchitecture) [2] https://www.anandtech.com/show/4455/amds-graphics-core-next-preview-amd-architects-for-compute/2 https://www.anandtech.com/show/4455/amds-graphics-core-next-...