Responses to this are IMHO unfair. In fact this isn't an inherently terrible or infeasible idea. Transistor costs for 4-bit BCD run just about at the ln(16)/l

Responses to this are IMHO unfair. In fact this isn't an inherently terrible or infeasible idea. Transistor costs for 4-bit BCD run just about at the ln(16)/ln(10) level you'd expect, and just a few gates of depth per digit are needed for the carry detect (something that can easily be folded into the carry lookahead optimizations all modern adders need anyway). Hardware multipliers would need more work, you can't make a Dadda/Wallace tree with anything but binary adders, but I'm sure there's a clever generalization. The one thing you'd lose would be two's complement trickery. Addition and subtraction in BCD actually are fundamentally different algorithms, so that's something to worry about. But then signedness mismatches are themselves a historical footgun, so you could spin this away too, I think. But... beyond that this could absolutely be done. And it's also true that a lot of traditional bugs with FPU/brain precision mismatch would be fixed in the process. I don't know that it's an architecture I'd pick, but it's not something to reject out of hand either. It's worth discussing and not downvoting.