It sounds like my understanding might be incomplete, could you expand on your comment? IIRC, IEEE-754 includes several options for what should happen when vari

It sounds like my understanding might be incomplete, could you expand on your comment? IIRC, IEEE-754 includes several options for what should happen when various operations consume or could create NaN values. (As well as underflow, overflow, etc.) But that all of those options are covered by the spec. So, e.g., a modern x86-64 processor supports various FP modes (NaN signalling, etc.), and all of those FP modes result in behavior that's well-defined by IEEE-754. Is that not the case? EDIT: TIL about "NaN payloads". Now the parent comment makes more sense to me.